This invention relates to a process for forming high performance integrated circuit devices, and more particularly, to a process for forming self-aligned and low resistance contacts to P type regions in a semiconductor substrate constituting the integrated circuit.
As used herein, a P type region includes the following: In the case of a single vertical NPN transistor formed in a semiconductor body, it designates the base of the transistor; in the case of a complementary vertical NPN device and lateral PNP (hereafter, LPNP) transistor, P type region includes the base of the NPN, collector or emitter of LPNP and resistors (if resistors are integrated into the complementary circuit); and in the case of complementary field effect transistors (FET), the P type region is the source or drain of the PFET.
Focussing for discussion purposes on the fabrication of a single vertical NPN transistor, briefly, referring to FIG. 1, the conventional method of forming the device consists of forming an N+ subcollector 12 on a P- silicon substrate 10. An N type epitaxial silicon layer 14 is then formed followed by introducing P type (e.g., boron) dopant into a selected region of layer 14 to a peak concentration of about (1-5).times.10.sup.18 atoms/cc to form the transistor base 16. The structure is then thermally oxidized to form a silicon dioxide 18. Silicon nitride 20 is additionally formed over the entire structure. An opening is then made in the oxide and nitride layers overlying a portion of the base diffusion 16 and N type dopant (e.g., arsenic) is introduced into the exposed base region to form the emitter 22. Finally, contact opening is made in the oxide-nitride insulator over the base and conductive metallurgical contacts 24 and 26 are established with the base and emitter regions, respectively. Suitable device isolation (such as recessed isolation or trench isolation) is also formed during the course of the device fabrication. U.S. Pat. Nos. 4,014,718 issued to Tomozawa et al and 4,032,957 issued to Yagi et al are illustrative of this prior art practice.
Referring to the structure shown in FIG. 1, the NPN transistor is characterized by a base series resistance Rb which consists of roughly three components: (1) the intrinsic base resistance Rbi which designates the resistance of the base portion lying directly beneath the emitter 22; (2) the extrinsic base resistance Rbe which is the resistance of the base portion which resides between the edge of the emitter/base junction 28 and the edge of the contact 24; and the base contact resistance Rbc which is the resistance incurred due to making metallurgical contact to the base surface region. To a first approximation, the mathematical relationship between Rb and its components may be expressed as EQU Rb=Rbc+Rbe+Rbi
With ever-increasing demands placed on circuit performance (speed of operation) particularly in the case of bipolar logic applications such as current switch, emitter-follower or bipolar array circuits, it is imperative that Rb be rendered as low as possible. Also, as the operation current levels in these circuits increase the impact of Rb on the circuit performance increases proportionally.
A basic deficiency of the prior art bipolar device fabrication discussed hereinabove is that during the thermal oxidation step to form the oxide layer 18, the P type (boron) dopant, due to its high segregation coefficient, rapidly segregates into the oxide layer 18. This, in turn, depletes the surface concentration of P dopant in the base surface resulting in a significant increase in the contact resistance component Rbc of the base series resistance Rb after the contact metallurgy 24 is formed.
As microelectronics industry evolves into the very large scale integration (VLSI) and ultra large scale integration (ULSI) eras by shrinking the device sizes, the resistance components Rbi and Rbe correspondingly decrease (assuming that the base and emitter regions are doped to optimal concentration levels). However, since the size of the device contacts cannot be reduced indefinitely, in this situation the resistance associated with the metal-silicon interface, Rbc, becomes, by far, the dominant component. Thus, it is imperative that Rbc be reduced consistent with the requirements of VLSI and ULSI circuit applications.
It would appear that one method of reducing Rbc is to dope the base region at the outset to an excessively high concentration level (e.g., solid solubility limit of boron in silicon). However, during the various subsequent thermal steps, the dopant will be pushed excessively deep increasing the base-collector capacitance which renders the device slow. Another disadvantage of such excessive blanket doping of the base region is creation of a leaky emitter-base junction 28.
An alternative method of reducing Rbc would appear to be utilization of a blockout mask to selectively introduce additional dopant into the base contact region following the emitter fabrication to compensate for the segregated dopant therein. However, this requires not only an extra mask step which adds to the process complexity, but also may result in higher Rbe due to an increase in the separation between the emitter and base contact brought about by two edge-to-edge tolerances corresponding to the opening in mask used to form the emitter and the opening in the extra mask under consideration. Also, this method will increase the total area of the base which leads to increased collector-base capacitance thereby further slowing the device. In this connection reference is made to U.S. Pat. No. 4,385,433 issued to Ozawa for its disclosure of P+ contact implant utilizing a photolithographic mask to avoid doping of N epitaxial regions (i.e., Schottky diode anodes).
Yet another method of reducing the base contact resistance is by utilization of a polysilicon base contact. Representative of this basic method is U.S. Pat. No. 4,125,426 issued to Inayoshi et al. In this process, typically, a polysilicon layer doped the solid solubility limit is formed over the entire base region immediately after the base fabrication to prevent segregation of P dopant from the base. The polysilicon is then patterned in a desired shape followed by making an opening in the polysilicon corresponding to the emitter region and embedding the emitter in a portion of the base region by introducing N type dopant therethrough. Thereafter, base contact opening is formed in the polysilicon and contact metallurgy is established with all elements of the transistor. This process, although lowering Rbc without increasing Rbe, requires two additional masks (one to open the region for the base and the second to define the polysilicon). Also, additional insulator layer formation and reactive ion etching (RIE) steps will be necessitated. This process also gives rise to undesirable device topology (consisting of deep valleys and high hills) since the polysilicon (to render its resistance low) is made sufficiently thick and subsequently coated with passivation layers. This topology is prone to introducing serious metallization problems.
The present invention overcomes these and other deficiencies of the prior art by means of a simple and straight forward process which guarantees low P contact resistance.
It is an object of the invention to selectively introduce P dopant into the P contact regions after completion of all thermal process steps to replenish the dopant loss therein during prior thermal process steps.
It is another object of the invention to achieve the aforementioned objective by taking advantage of the phenomenon that N+ doped regions oxidize at low temperatures at a preferentially high rate compared to P doped regions.